Automatically Accelerating Non-Numerical Programs by Architecture-Compiler Co-Design. - Campanoni, Simone; Brownell, Kevin; Kanev, Svilen; Jones, Timothy M.; Gu-Yeon Wei; Brooks, David (Communications of the ACM, 2017)
Because of the high cost of communication between processors, compilers that parallelize loops automatically have been forced to skip a large class of loops that are both critical to performance and rich in latent parallelism. HELIX-RC is a compiler/microprocessor co-design that opens those loops to parallelization by decoupling communication from thread execution in conventional multicore architecures. Simulations of HELIX-RC, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks.