Investigation of a novel common subexpression elimination method for low power and area efficient DCT architecture.
A wide interest has been observed to find a low power and area efficient hardware design of discrete cosine transform (DCT) algorithm. This research work proposed a novel Common Subexpression Elimination (CSE) based pipelined architecture for DCT, aimed at reproducing the cost metrics of power and a...
| Publicado en: | Scientific World Journal pp. 620868 - 620869 |
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| Autores principales: | , , , |
| Formato: | research Journal Article |
| Publicado: |
Wiley-Blackwell
2014
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| Acceso en línea: | Ver este registro en EBSCOhost |