The CONNECT Network-on-Chip Generator.
Efficiently supporting the communication needs of systems on chip with tens to hundreds of interacting modules requires a systematic and flexible network-on-chip (NoC) infrastructure. The freely available CONNECT generator lets users quickly navigate a range of design parameters to produce tailored...
| Publicado en: | Computer (00189162) Vol. 48; no. 12; pp. 72 - 80 |
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| Autores principales: | , |
| Formato: | Artículo |
| Publicado: |
IEEE
Dec2015
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| Materias: | |
| Acceso en línea: | Ver este registro en EBSCOhost |
| fields | @attributes: recordID: 1 pdfLink: plink: https://search.ebscohost.com/login.aspx?direct=true&db=hlh&AN=112077659&site=ehost-live header: @attributes: shortDbName: hlh uiTerm: 112077659 longDbName: Humanities International Complete uiTag: AN controlInfo: bkinfo: jinfo: jid: 00189162 PUT jtl: Computer (00189162) issn: 00189162 maglogo: N pubinfo: dt: Dec2015 vid: 48 iid: 12 pid: 13605 pub: IEEE artinfo: ui: 112077659 10.1109/MC.2015.378 ppf: 72 ppct: 8 formats: tig: atl: The CONNECT Network-on-Chip Generator. aug: au: Papamichael, Michael K. Hoe, James C. affil: Microsoft Research Carnegie Mellon University su: Networks on a chip Verilog (Computer hardware description language) Computer hardware description languages Computer simulation of integrated circuits Computer systems sug: subj: Networks on a chip Verilog (Computer hardware description language) Computer hardware description languages Computer simulation of integrated circuits Computer systems keyword: chip design design synthesis Field programmable gate arrays Hardware Hardware design languages intellectual property interconnect design IP blocks network on chip Network topology Network-on-chip NoC Ports (Computers) scalable computing SoC system on chip Topology Verilog ab: Efficiently supporting the communication needs of systems on chip with tens to hundreds of interacting modules requires a systematic and flexible network-on-chip (NoC) infrastructure. The freely available CONNECT generator lets users quickly navigate a range of design parameters to produce tailored NoC design instances in Verilog. To date, it has generated nearly 4,000 designs. pubtype: Academic Journal doctype: Article src: R language: English refInfo: copyright: @attributes: flag: Y dt: @attributes: year: 2015 holdings: @attributes: islocal: N |
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