FPGA Implementation of Heart Rate Monitoring System.
This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to acc...
| Published in: | Journal of Medical Systems Vol. 40; no. 3; pp. 1 - 13 |
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| Main Authors: | , , |
| Format: | equations & formulas pictorial research tables/charts tracings Journal Article |
| Published: |
Springer Nature
Mar2016
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| Online Access: | View this record in EBSCOhost |
| fields | @attributes: recordID: 1 pdfLink: plink: https://search.ebscohost.com/login.aspx?direct=true&db=ccm&AN=115925271&site=ehost-live header: @attributes: shortDbName: ccm uiTerm: 115925271 longDbName: CINAHL Complete uiTag: AN controlInfo: bkinfo: dissinfo: jinfo: jid: 01485598 4N0 jtl: Journal of Medical Systems issn: 01485598 maglogo: N pubinfo: dt: Mar2016 vid: 40 iid: 3 pid: 237 pub: Springer Nature place: New York, New York artinfo: ui: 115925271 115925271 115925271 10.1007/s10916-015-0410-4 115925271 ppf: 1 ppct: 12 formats: fmt: @attributes: type: P tig: atl: FPGA Implementation of Heart Rate Monitoring System. aug: au: Panigrahy, D. Rakshit, M. Sahu, P. affil: Department of Electrical Engineering, NIT Rourkela, Odisha India sug: subj: Heart Rate Monitoring, Physiologic Methods Electrocardiography Technology, Medical Evaluation Computing Methodologies Algorithms Utilization ab: This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84 %, the sensitivity of 99.94 % and the positive predictive value of 99.89 %. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA. pubtype: Academic Journal doctype: equations & formulas pictorial research tables/charts tracings Journal Article ougenre: Article language: English refInfo: holdings: @attributes: islocal: N |
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