Defying Moore: Envisioning the Economics of a Semiconductor Revolution through 12nm Specialization.
This article investigates whether new artificial intelligence (AI) chips can be built at 12nm technology and exceed or at least match chips made at 5nm or lower. The authors cite the four trends in the semiconductor industry including the perceived end of Moore’s law when investigating technology sc...
| Published in: | Communications of the ACM Vol. 68; no. 7; pp. 108 - 120 |
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| Main Authors: | , |
| Format: | Article |
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Association for Computing Machinery
Jul2025
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| Subjects: | |
| Online Access: | View this record in EBSCOhost |
| fields | @attributes: recordID: 1 pdfLink: plink: https://search.ebscohost.com/login.aspx?direct=true&db=hlh&AN=186249322&site=ehost-live header: @attributes: shortDbName: hlh uiTerm: 186249322 longDbName: Humanities International Complete uiTag: AN controlInfo: bkinfo: jinfo: jid: 00010782 ACM jtl: Communications of the ACM issn: 00010782 maglogo: N pubinfo: dt: Jul2025 vid: 68 iid: 7 pid: 68 pub: Association for Computing Machinery artinfo: ui: 186249322 10.1145/3711920 ppf: 108 ppct: 12 formats: tig: atl: Defying Moore: Envisioning the Economics of a Semiconductor Revolution through 12nm Specialization. aug: au: Davies, Michael Sankaralingam, Karthikeyan affil: University of Wisconsin-Madison, Computer Sciences, Madison, Wisconsin, United States su: Semiconductor design Semiconductor industry Technological innovations Computer architecture Moore's law Economics Graphics processing units Bandwidths Sustainability sug: subj: Semiconductor design Semiconductor industry Technological innovations Computer architecture Moore's law Economics Graphics processing units Bandwidths Sustainability ab: This article investigates whether new artificial intelligence (AI) chips can be built at 12nm technology and exceed or at least match chips made at 5nm or lower. The authors cite the four trends in the semiconductor industry including the perceived end of Moore’s law when investigating technology scaling and architectural innovation. This research presents tiled decoupled control and compute (TDCC) architecture with Galileo as an example and compares it to others with TDCC, including SIGMA, as well as Nvidia’s graphics processing unit (GPU). pubtype: Periodical doctype: Article src: R language: English refInfo: copyright: @attributes: flag: Y dt: @attributes: year: 2025 holdings: @attributes: islocal: N |
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