Maximizing Power Efficiency with Asymmetric Multicore Systems.
The article discusses the development of software that takes advantage of the design of asymmetric multicore processors (AMPs). The potential for AMPs to conserve large amounts of electricity due to their design, which consists of cores using the same instruction set architecture (ISA) but with diff...
| Publicado en: | Communications of the ACM Vol. 52; no. 12; pp. 48 - 58 |
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| Autores principales: | , , , |
| Formato: | Artículo |
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Association for Computing Machinery
Dec2009
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| Materias: | |
| Acceso en línea: | Ver este registro en EBSCOhost |
| fields | @attributes: recordID: 1 pdfLink: plink: https://search.ebscohost.com/login.aspx?direct=true&db=hlh&AN=45580308&site=ehost-live header: @attributes: shortDbName: hlh uiTerm: 45580308 longDbName: Humanities International Complete uiTag: AN controlInfo: bkinfo: jinfo: jid: 00010782 ACM jtl: Communications of the ACM issn: 00010782 maglogo: N pubinfo: dt: Dec2009 vid: 52 iid: 12 pid: 68 pub: Association for Computing Machinery artinfo: ui: 45580308 10.1145/1610252.1610270 ppf: 48 ppct: 10 formats: tig: atl: Maximizing Power Efficiency with Asymmetric Multicore Systems. aug: au: FEDOROVA, ALEXANDRA SAEZ, JUAN CARLOS SHELEPOV, DANIEL PRIETO, MANUEL affil: Assistant professor of computer science, Simon Fraser University, Vancouver, Canada. Complutense University, Madrid. Member, Internet Explorer team, Microsoft, Redmond, WA. Associate professor, department of computer architecture, Complutense University, Madrid. su: Microprocessors High performance processors Parallel processing Computer architecture Threads (Computer programs) Electric power conservation Computer science sug: subj: Microprocessors High performance processors Parallel processing Computer architecture Threads (Computer programs) Electric power conservation Computer science ab: The article discusses the development of software that takes advantage of the design of asymmetric multicore processors (AMPs). The potential for AMPs to conserve large amounts of electricity due to their design, which consists of cores using the same instruction set architecture (ISA) but with differing performance and power characteristics, is discussed. The inclusion of several powerful, high-power-consumption cores along with a large number of slower, low-power-consumption cores in the design of an AMP is mentioned, noting that processor-intensive, single-threaded, sequential tasks are best served by the more powerful cores while parallel applications run most efficiently on the large number of simpler cores. pubtype: Periodical doctype: Article src: R language: English refInfo: copyright: @attributes: flag: Y dt: @attributes: year: 2009 holdings: @attributes: islocal: N |
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