Reflection reduction on DDR3 high-speed bus by improved PSO.
The signal integrity of the circuit, as one of the important design issues in high-speed digital system, is usually seriously affected by the signal reflection due to impedance mismatch in the DDR3 bus. In this paper, a novel optimization method is proposed to optimize impedance mismatch and reduce...
| Publicado en: | Scientific World Journal pp. 257972 - 257973 |
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| Autores principales: | , , , |
| Formato: | research Journal Article |
| Publicado: |
Wiley-Blackwell
2014
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| Acceso en línea: | Ver este registro en EBSCOhost |