Real-Time Computing on Multicore Processors.

Architects of multicore chips for avionics must define and bound intercore interference, which requires assuming a constant worst-case execution time for tasks executing on the chip. With the Single Core Equivalent technology package, engineers can treat each core as if it were a single-core chip.

Detalles Bibliográficos
Publicado en:	Computer (00189162) Vol. 49; no. 9; pp. 69 - 78
Autores principales:	Sha, Lui, Caccamo, Marco, Mancuso, Renato, Kim, Jung-Eun, Yoon, Man-Ki, Pellizzoni, Rodolfo, Yun, Heechul, Kegley, Russell B., Perlman, Dennis R., Arundale, Greg, Bradford, Richard
Formato:	Artículo
Publicado:	IEEE Sep2016
Materias:	Real-time computing Multicore processors Avionics Information & communication technologies Mathematical bounds
Acceso en línea:	Ver este registro en EBSCOhost

Descripción
Sumario:	Architects of multicore chips for avionics must define and bound intercore interference, which requires assuming a constant worst-case execution time for tasks executing on the chip. With the Single Core Equivalent technology package, engineers can treat each core as if it were a single-core chip.