Real-Time Computing on Multicore Processors.
Architects of multicore chips for avionics must define and bound intercore interference, which requires assuming a constant worst-case execution time for tasks executing on the chip. With the Single Core Equivalent technology package, engineers can treat each core as if it were a single-core chip.
| Publicado en: | Computer (00189162) Vol. 49; no. 9; pp. 69 - 78 |
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| Autores principales: | , , , , , , , , , , |
| Formato: | Artículo |
| Publicado: |
IEEE
Sep2016
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| Materias: | |
| Acceso en línea: | Ver este registro en EBSCOhost |
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