Low Power Circuit Design For Footed Quasi Resistance Scheme In 45nm Vlsi Technology-Review.
This paper provides detailed information about earlier research works focused on designing and implementing VLSI circuits in terms of power consumption and leakage reduction through various CMOS based methods. A few existing exploration works were centered on diminishing the power spillage in CMOS c...
| Publicado en: | Turkish Journal of Physiotherapy Rehabilitation Vol. 32; no. 2; pp. 407 - 422 |
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| Autores principales: | , , |
| Formato: | review tables/charts Journal Article |
| Publicado: |
Turkish Journal of Physiotherapy & Rehabilitation
2021
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| Acceso en línea: | Ver este registro en EBSCOhost |
| fields | @attributes: recordID: 1 pdfLink: plink: https://search.ebscohost.com/login.aspx?direct=true&db=ccm&AN=151005983&site=ehost-live header: @attributes: shortDbName: ccm uiTerm: 151005983 longDbName: CINAHL Complete uiTag: AN controlInfo: bkinfo: dissinfo: jinfo: jid: 13008757 YU1 jtl: Turkish Journal of Physiotherapy Rehabilitation issn: 13008757 maglogo: N pubinfo: dt: 2021 vid: 32 iid: 2 pid: 20392 pub: Turkish Journal of Physiotherapy & Rehabilitation place: Kizilay/ Ankara, <Blank> artinfo: ui: 151005983 151005983 151005983 151005983 ppf: 407 ppct: 15 formats: fmt: @attributes: type: P tig: atl: Low Power Circuit Design For Footed Quasi Resistance Scheme In 45nm Vlsi Technology-Review. aug: au: Satyanarayana, Telugu Tiwari, Mukesh Reddy, Vundela Padmanabha affil: Department of Electronics and Communication Engineering, Sri Satya Sai University of Technology and Medical Sciences, Sehore, Bhopal-Indore Road, Madhya Pradesh, India sug: subj: Electricity Technology Computer-Aided Design ab: This paper provides detailed information about earlier research works focused on designing and implementing VLSI circuits in terms of power consumption and leakage reduction through various CMOS based methods. A few existing exploration works were centered on diminishing the power spillage in CMOS circuits. Some of them are offered here to comprehend the issues confronted and the fitting arrangements required. Most of the existing methods are developed based on the Domino logic. But, Addition of static inverter is used in the domino logic circuit to eliminate the logic 1 (in precharge phase) to logic 0 (in evaluation phase) transition. This elimination of transition from logic 1 to logic 0 signifies that additional charging and discharging is performed at the output capacitance of static inverter when it is in precharge phase and meanwhile the output of its subsequent evaluation phase is logic 0, which causes significant power dissipation. Thus this paper conducted the detailed literature survey to overcome this power dissipation problem. This problem is solved through various techniques, whereby the pseudo dynamic buffer (PDB) model significantly reduces power dissipation and hence saves power. However, in the PDB model we have logic 1 (in precharge) to logic 0 (in evaluation) transition which results in faulty output when used for designing of cascaded circuits. Thus, to slove this problem, this survey identified Footed Quasi resistance (FQR) is prominent solution as compared to the PDB model, FQR topology solves the problems caused due to cascading. Moreover, FQR model has lower power dissipation as compared to domino logic model. pubtype: Academic Journal doctype: review tables/charts Journal Article ougenre: Article language: English refInfo: holdings: @attributes: islocal: N |
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