Implementation Of Fast Binary Sorting Network Generated By Counters.

Parallel counters play an important role in many circuits that manipulate numbers, especially fast multipliers. Part of the crucial route in many DSP components is the parallel summing of several operands. High ratios of compression counters & compressors are required to speed up the totaling proces...

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Publicado en:Journal of Namibian Studies Vol. 33; pp. 756 - 768
Autores principales: VAISHNAVI, A., NARAYANA, M.
Formato: Artículo
Publicado: Society of Cultural Studies & Social Sciences 2023 Supplement
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Acceso en línea:Ver este registro en EBSCOhost
fields @attributes:
  recordID: 1
pdfLink:
plink: https://search.ebscohost.com/login.aspx?direct=true&db=hlh&AN=172998284&site=ehost-live
header:
  @attributes:
    shortDbName: hlh
    uiTerm: 172998284
    longDbName: Humanities International Complete
    uiTag: AN
  controlInfo:
    bkinfo:
    jinfo:
      jid:
        18635954
        G5EZ
      jtl: Journal of Namibian Studies
      issn: 18635954
      maglogo: N
    pubinfo:
      dt: 2023 Supplement
      vid: 33
      pid: 92471
      pub: Society of Cultural Studies & Social Sciences
    artinfo:
      ui: 172998284
      ppf: 756
      ppct: 12
      formats:
      tig:
        atl: Implementation Of Fast Binary Sorting Network Generated By Counters.
      aug:
        au:
          VAISHNAVI, A.
          NARAYANA, M.
        affil:
          M.TECH, ANURAG UNIVERSITY, Venkatapur, Ghatkesar, Medchal Dist-501301.
          PROFESSOR ANURAG UNIVERSITY, Venkatapur, Ghatkesar, Medchal Dist-501301.
      su:
        Boolean expressions
        Parallel algorithms
        Compressors
      sug:
        subj:
          Boolean expressions
          Parallel algorithms
          Compressors
      keyword:
        Binary counter
        exact/approximate 4:2 compressor
        multiplier
        one-hot code
        sorting network
      ab: Parallel counters play an important role in many circuits that manipulate numbers, especially fast multipliers. Part of the crucial route in many DSP components is the parallel summing of several operands. High ratios of compression counters & compressors are required to speed up the totaling process. A new exact/approximate (4:2) compressor based on a sorting network is being developed for this project. Reordered sequences, which are uniquely portrayed through one-hot code sequences, are generated by feeding the counter's inputs into sorting networks in an asymmetric fashion. The counter's output Boolean expressions may be greatly simplified by using three specific Boolean equations created between the reorganized sequences on the one-hot code sequence. In addition, this undertaking is improved by developing scalable structures based on provided techniques for finding/sorting M biggest values from N inputs utilizing parallel sorting algorithms. The iterative sorting methods were also presented for locating the greatest values. The BUBBLE SORTING algorithm is one example of a parameteroptimized implementation of such an algorithm.
      pubtype: Academic Journal
      doctype: Article
      src: R
    language: English
    refInfo:
    copyright:
      @attributes:
        flag: Y
      dt:
        @attributes:
          year: 2023
    holdings:
      @attributes:
        islocal: N