New Technique Could Increase Chip Performance.

The article discusses a lithography technique under development at the Massachusetts Institute of Technology (MIT) that holds promise for creating grids of parallel lines on computer chips that are only 25 nanometers wide. Scanning-beam interference lithography (SBIL), developed by researchers under...

Descripción completa

Detalles Bibliográficos
Publicado en:Computer (00189162) Vol. 42; no. 3; pp. 21 - 23
Autor principal: Paulson, Linda Dailey
Formato: Artículo
Publicado: IEEE Mar2009
Materias:
Acceso en línea:Ver este registro en EBSCOhost
fields @attributes:
  recordID: 1
pdfLink:
plink: https://search.ebscohost.com/login.aspx?direct=true&db=hlh&AN=36948223&site=ehost-live
header:
  @attributes:
    shortDbName: hlh
    uiTerm: 36948223
    longDbName: Humanities International Complete
    uiTag: AN
  controlInfo:
    bkinfo:
    jinfo:
      jid:
        00189162
        PUT
      jtl: Computer (00189162)
      issn: 00189162
      maglogo: N
    pubinfo:
      dt: Mar2009
      vid: 42
      iid: 3
      pid: 13605
      pub: IEEE
    artinfo:
      ui: 36948223
      ppf: 21
      ppct: 2
      formats:
      tig:
        atl: New Technique Could Increase Chip Performance.
      aug:
        au: Paulson, Linda Dailey
      su:
        Integrated circuits
        Microprocessors
        Personal computers
        Massachusetts Institute of Technology
        Schattenburg, Mark
        Heilmann, Ralf
      sug:
        subj:
          Integrated circuits
          Microprocessors
          Personal computers
          Massachusetts Institute of Technology
          Schattenburg, Mark
          Heilmann, Ralf
      ab: The article discusses a lithography technique under development at the Massachusetts Institute of Technology (MIT) that holds promise for creating grids of parallel lines on computer chips that are only 25 nanometers wide. Scanning-beam interference lithography (SBIL), developed by researchers under Mark Schattenburg, is being implemented by another research team headed by Ralf Heilmann to generate the 25-nanometer patterns. By comparison, most chips use 65-nanometer patterns, with 45-nanometer designs just having begun to appear commercially in volume.
      pubtype: Academic Journal
      doctype: Article
      src: R
    language: English
    refInfo:
    copyright:
      @attributes:
        flag: Y
      dt:
        @attributes:
          year: 2009
    holdings:
      @attributes:
        islocal: N