The Bulk Multicore Architecture for Improved Programmability.

The article presents a general-purpose multicore processor architecture called the Bulk Multicore, which is optimized for maximum programmability. The need for hardware architecture to enable a programmable environment is noted, mentioning that programmability should ensure that the architecture is...

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Publicado en:Communications of the ACM Vol. 52; no. 12; pp. 58 - 66
Autores principales: TORRELAS, JOSEP, CEZE, LUIS, TUCK, JAMES, CASCAVAL, CALIN, INOS, PABLO MONTES, AHN, WONSUN, PRVULOVIC, MILOS
Formato: Artículo
Publicado: Association for Computing Machinery Dec2009
Materias:
Acceso en línea:Ver este registro en EBSCOhost
fields @attributes:
  recordID: 1
pdfLink:
plink: https://search.ebscohost.com/login.aspx?direct=true&db=hlh&AN=45580309&site=ehost-live
header:
  @attributes:
    shortDbName: hlh
    uiTerm: 45580309
    longDbName: Humanities International Complete
    uiTag: AN
  controlInfo:
    bkinfo:
    jinfo:
      jid:
        00010782
        ACM
      jtl: Communications of the ACM
      issn: 00010782
      maglogo: N
    pubinfo:
      dt: Dec2009
      vid: 52
      iid: 12
      pid: 68
      pub: Association for Computing Machinery
    artinfo:
      ui:
        45580309
        10.1145/1610252.1610271
      ppf: 58
      ppct: 8
      formats:
      tig:
        atl: The Bulk Multicore Architecture for Improved Programmability.
      aug:
        au:
          TORRELAS, JOSEP
          CEZE, LUIS
          TUCK, JAMES
          CASCAVAL, CALIN
          INOS, PABLO MONTES
          AHN, WONSUN
          PRVULOVIC, MILOS
        affil:
          Professor and Willett Faculty Scholar, Department of Computer Science, University of Illinois, Urbana-Champaign.
          Assistant professor, Department of Computer Science and Engineering, University of Washington, Seattle, WA.
          Assistant professor, Department of Electrical and Computer Engineering, North Carolina State University, Raleigh, NC.
          Research staff member and manager of programming models and tools for scalable systems, IBM T.J. Watson Research Center, Yorktown Heights, NY.
          Staff engineer, Multicore Research Group, Samsung Information Systems America, San Jose, CA.
          Department of Computer Science, University of Illinois, Urbana-Champaign.
          Associate professor, School of Computer Science, College of Computing, Georgia Institute of Technology, Atlanta, GA.
      su:
        Computer architecture
        Multiprocessors
        Microprocessor programming
        Parallel processing
        Parallel programming
        Scalability
      sug:
        subj:
          Computer architecture
          Multiprocessors
          Microprocessor programming
          Parallel processing
          Parallel programming
          Scalability
      ab: The article presents a general-purpose multicore processor architecture called the Bulk Multicore, which is optimized for maximum programmability. The need for hardware architecture to enable a programmable environment is noted, mentioning that programmability should ensure that the architecture is capable of high efficiency without requiring the programmer to manage low-level tasks and that the potential for parallel programming errors is minimized. The Bulk Multicore's satisfaction of these needs is described, noting its novel support for scalable hardware cache coherence, its inclusion of high-performance sequential memory consistency, and its introduction of novel hardware primitives that can support the building of an advanced program development and debugging environment.
      pubtype: Periodical
      doctype: Article
      src: R
    language: English
    refInfo:
    copyright:
      @attributes:
        flag: Y
      dt:
        @attributes:
          year: 2009
    holdings:
      @attributes:
        islocal: N