Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks.
Future scalability for kilo-core architectures requires solutions beyond the capabilities of protocol and software design. Single-cycle multihop asynchronous repeated traversal (SMART) creates virtual single-cycle paths across the shared network between cores, potentially offering significant reduct...
| Publicado en: | Computer (00189162) Vol. 46; no. 10; pp. 48 - 56 |
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| Autores principales: | , , , , , , |
| Formato: | Artículo |
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IEEE
Oct2013
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| Materias: | |
| Acceso en línea: | Ver este registro en EBSCOhost |
| fields | @attributes: recordID: 1 pdfLink: plink: https://search.ebscohost.com/login.aspx?direct=true&db=hlh&AN=91789889&site=ehost-live header: @attributes: shortDbName: hlh uiTerm: 91789889 longDbName: Humanities International Complete uiTag: AN controlInfo: bkinfo: jinfo: jid: 00189162 PUT jtl: Computer (00189162) issn: 00189162 maglogo: N pubinfo: dt: Oct2013 vid: 46 iid: 10 pid: 13605 pub: IEEE artinfo: ui: 91789889 10.1109/MC.2013.260 ppf: 48 ppct: 8 formats: tig: atl: Single-Cycle Multihop Asynchronous Repeated Traversal: A SMART Future for Reconfigurable On-Chip Networks. aug: au: Krishna, Tushar Chen, Chia-Hsin Owen Park, Sunghyun Kwon, Woo-Cheol Subramanian, Suvinay Chandrakasan, Anantha P. Peh, Li-Shiuan affil: MIT su: Scalability Software architecture Computer network protocols Systems design Asynchronous circuits sug: subj: Scalability Software architecture Computer network protocols Systems design Asynchronous circuits keyword: cache coherence traffic Clocks Computers Delays efficient network design interconnection network multicore architecture network-on-chip NoC on-chip latency parallel computer architecture Ports (Computers) private L2 Repeaters scalability scalable networks shared L2 SoC System-on-chip Wires ab: Future scalability for kilo-core architectures requires solutions beyond the capabilities of protocol and software design. Single-cycle multihop asynchronous repeated traversal (SMART) creates virtual single-cycle paths across the shared network between cores, potentially offering significant reductions in runtime latency and energy expenditure. pubtype: Academic Journal doctype: Article src: R language: English refInfo: copyright: @attributes: flag: Y dt: @attributes: year: 2013 holdings: @attributes: islocal: N |
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