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Automatically Accelerating Non-Numerical Programs by Architecture-Compiler Co-Design.

Because of the high cost of communication between processors, compilers that parallelize loops automatically have been forced to skip a large class of loops that are both critical to performance and rich in latent parallelism. HELIX-RC is a compiler/microprocessor co-design that opens those loops to...

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Publicado en:Communications of the ACM Vol. 60; no. 12; pp. 88 - 98
Autores principales: Campanoni, Simone, Brownell, Kevin, Kanev, Svilen, Jones, Timothy M., Gu-Yeon Wei, Brooks, David
Formato: Artículo
Publicado: Association for Computing Machinery Dec2017
Materias:
Parallel computer software
Parallelizing compilers
Microprocessor design & construction
Multicore processors
Computer architecture
Acceso en línea:Ver este registro en EBSCOhost
Sumario:Because of the high cost of communication between processors, compilers that parallelize loops automatically have been forced to skip a large class of loops that are both critical to performance and rich in latent parallelism. HELIX-RC is a compiler/microprocessor co-design that opens those loops to parallelization by decoupling communication from thread execution in conventional multicore architecures. Simulations of HELIX-RC, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks.