Automatically Accelerating Non-Numerical Programs by Architecture-Compiler Co-Design.
Because of the high cost of communication between processors, compilers that parallelize loops automatically have been forced to skip a large class of loops that are both critical to performance and rich in latent parallelism. HELIX-RC is a compiler/microprocessor co-design that opens those loops to...
| Publicado en: | Communications of the ACM Vol. 60; no. 12; pp. 88 - 98 |
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| Autores principales: | , , , , , |
| Formato: | Artículo |
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Association for Computing Machinery
Dec2017
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| Materias: | |
| Acceso en línea: | Ver este registro en EBSCOhost |
| fields | @attributes: recordID: 1 pdfLink: plink: https://search.ebscohost.com/login.aspx?direct=true&db=hlh&AN=126581922&site=ehost-live header: @attributes: shortDbName: hlh uiTerm: 126581922 longDbName: Humanities International Complete uiTag: AN controlInfo: bkinfo: jinfo: jid: 00010782 ACM jtl: Communications of the ACM issn: 00010782 maglogo: N pubinfo: dt: Dec2017 vid: 60 iid: 12 pid: 68 pub: Association for Computing Machinery artinfo: ui: 126581922 10.1145/3139461 ppf: 88 ppct: 10 formats: tig: atl: Automatically Accelerating Non-Numerical Programs by Architecture-Compiler Co-Design. aug: au: Campanoni, Simone Brownell, Kevin Kanev, Svilen Jones, Timothy M. Gu-Yeon Wei Brooks, David affil: Northwestern University, Evanston, IL Harvard University, Cambridge, MA University of Cambridge, England su: Parallel computer software Parallelizing compilers Microprocessor design & construction Multicore processors Computer architecture sug: subj: Parallel computer software Parallelizing compilers Microprocessor design & construction Multicore processors Computer architecture ab: Because of the high cost of communication between processors, compilers that parallelize loops automatically have been forced to skip a large class of loops that are both critical to performance and rich in latent parallelism. HELIX-RC is a compiler/microprocessor co-design that opens those loops to parallelization by decoupling communication from thread execution in conventional multicore architecures. Simulations of HELIX-RC, applied to a processor with 16 Intel Atom-like cores, show an average of 6.85× performance speedup for six SPEC CINT2000 benchmarks. pubtype: Periodical doctype: Article src: R language: English refInfo: copyright: @attributes: flag: Y dt: @attributes: year: 2017 holdings: @attributes: islocal: N |
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