| Sumario: | The article discusses a lithography technique under development at the Massachusetts Institute of Technology (MIT) that holds promise for creating grids of parallel lines on computer chips that are only 25 nanometers wide. Scanning-beam interference lithography (SBIL), developed by researchers under Mark Schattenburg, is being implemented by another research team headed by Ralf Heilmann to generate the 25-nanometer patterns. By comparison, most chips use 65-nanometer patterns, with 45-nanometer designs just having begun to appear commercially in volume.
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