Toward a Coherent Multicore Memory Model.
With exascale multicores, the question of how to efficiently support a shared memory model is of paramount importance. As programmers demand the convenience of coherent shared memory, ever-growing core counts place higher demands on memory subsystems, and increasing on-chip distances mean that inter...
| Publicado en: | Computer (00189162) Vol. 46; no. 10; pp. 30 - 32 |
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| Autor principal: | |
| Formato: | Artículo |
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IEEE
Oct2013
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| Acceso en línea: | Ver este registro en EBSCOhost |
| Sumario: | With exascale multicores, the question of how to efficiently support a shared memory model is of paramount importance. As programmers demand the convenience of coherent shared memory, ever-growing core counts place higher demands on memory subsystems, and increasing on-chip distances mean that interconnect delays exert a significant effect on memory access latencies. |
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