Toward a Coherent Multicore Memory Model.
With exascale multicores, the question of how to efficiently support a shared memory model is of paramount importance. As programmers demand the convenience of coherent shared memory, ever-growing core counts place higher demands on memory subsystems, and increasing on-chip distances mean that inter...
| Publicado en: | Computer (00189162) Vol. 46; no. 10; pp. 30 - 32 |
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| Formato: | Artículo |
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IEEE
Oct2013
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| Acceso en línea: | Ver este registro en EBSCOhost |
| fields | @attributes: recordID: 1 pdfLink: plink: https://search.ebscohost.com/login.aspx?direct=true&db=hlh&AN=91789907&site=ehost-live header: @attributes: shortDbName: hlh uiTerm: 91789907 longDbName: Humanities International Complete uiTag: AN controlInfo: bkinfo: jinfo: jid: 00189162 PUT jtl: Computer (00189162) issn: 00189162 maglogo: N pubinfo: dt: Oct2013 vid: 46 iid: 10 pid: 13605 pub: IEEE artinfo: ui: 91789907 10.1109/MC.2013.373 ppf: 30 ppct: 2 formats: tig: atl: Toward a Coherent Multicore Memory Model. aug: au: Devadas, Srinivas affil: MIT su: Multicore processors Distributed shared memory Integrated circuit interconnections sug: subj: Multicore processors Distributed shared memory Integrated circuit interconnections keyword: cache coherence directory protocol multicore architecture on-chip network soft errors ab: With exascale multicores, the question of how to efficiently support a shared memory model is of paramount importance. As programmers demand the convenience of coherent shared memory, ever-growing core counts place higher demands on memory subsystems, and increasing on-chip distances mean that interconnect delays exert a significant effect on memory access latencies. pubtype: Academic Journal doctype: Article src: R language: English refInfo: copyright: @attributes: flag: Y dt: @attributes: year: 2013 holdings: @attributes: islocal: N |
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