Toward a Coherent Multicore Memory Model.

With exascale multicores, the question of how to efficiently support a shared memory model is of paramount importance. As programmers demand the convenience of coherent shared memory, ever-growing core counts place higher demands on memory subsystems, and increasing on-chip distances mean that inter...

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Bibliographic Details
Published in:	Computer (00189162) Vol. 46; no. 10; pp. 30 - 32
Main Author:	Devadas, Srinivas
Format:	Article
Published:	IEEE Oct2013
Subjects:	Multicore processors Distributed shared memory Integrated circuit interconnections
Online Access:	View this record in EBSCOhost

Description
Summary:	With exascale multicores, the question of how to efficiently support a shared memory model is of paramount importance. As programmers demand the convenience of coherent shared memory, ever-growing core counts place higher demands on memory subsystems, and increasing on-chip distances mean that interconnect delays exert a significant effect on memory access latencies.