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Toward Holistic Soft-Error-Resilient Shared-Memory Multicores.

A proposed lightweight, soft-error-resilient architecture for shared-memory multicores enables cores to autonomously perform redundant execution of uninterrupted instruction sequences. The distributed redundancy control mechanism operates in concert with the coherence protocol to provide resiliency...

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Published in:Computer (00189162) Vol. 46; no. 10; pp. 56 - 65
Main Authors: Shi, Qingchuan, Khan, Omer
Format: Article
Published: IEEE Oct2013
Subjects:
Computer architecture
Fault-tolerant computing
Multicore processors
Distributed shared memory
Distributed computing
Online Access:View this record in EBSCOhost
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      dt: Oct2013
      vid: 46
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      pub: IEEE
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        10.1109/MC.2013.262
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        atl: Toward Holistic Soft-Error-Resilient Shared-Memory Multicores.
      aug:
        au:
          Shi, Qingchuan
          Khan, Omer
        affil: University of Connecticut
      su:
        Computer architecture
        Fault-tolerant computing
        Multicore processors
        Distributed shared memory
        Distributed computing
      sug:
        subj:
          Computer architecture
          Fault-tolerant computing
          Multicore processors
          Distributed shared memory
          Distributed computing
      keyword:
        Amplitude modulation
        Coherence
        Hardware
        hardware resiliency
        Multicore processing
        multicore processors
        Protocols
        Redundancy
        redundant execution
        Registers
        shared memory
        soft errors
      ab: A proposed lightweight, soft-error-resilient architecture for shared-memory multicores enables cores to autonomously perform redundant execution of uninterrupted instruction sequences. The distributed redundancy control mechanism operates in concert with the coherence protocol to provide resiliency for both computation and communication hardware. The Web extra at http://youtu.be/9A3oiIerI0w is a video interview in which guest editor Srinivas Devadas and author Omer Khan expand on how a proposed lightweight, soft-error-resilient architecture for shared-memory multicores enables cores to autonomously perform redundant execution of uninterrupted instruction sequences.
      pubtype: Academic Journal
      doctype: Article
      src: R
    language: English
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