Cover Image
QR Code

Toward Holistic Soft-Error-Resilient Shared-Memory Multicores.

A proposed lightweight, soft-error-resilient architecture for shared-memory multicores enables cores to autonomously perform redundant execution of uninterrupted instruction sequences. The distributed redundancy control mechanism operates in concert with the coherence protocol to provide resiliency...

Full description

Published in:Computer (00189162) Vol. 46; no. 10; pp. 56 - 65
Main Authors: Shi, Qingchuan, Khan, Omer
Format: Article
Published: IEEE Oct2013
Subjects:
Computer architecture
Fault-tolerant computing
Multicore processors
Distributed shared memory
Distributed computing
Online Access:View this record in EBSCOhost

Internet

View this record in EBSCOhost