Toward Holistic Soft-Error-Resilient Shared-Memory Multicores.

A proposed lightweight, soft-error-resilient architecture for shared-memory multicores enables cores to autonomously perform redundant execution of uninterrupted instruction sequences. The distributed redundancy control mechanism operates in concert with the coherence protocol to provide resiliency...

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Detalles Bibliográficos

Publicado en:	Computer (00189162) Vol. 46; no. 10; pp. 56 - 65
Autores principales:	Shi, Qingchuan, Khan, Omer
Formato:	Artículo
Publicado:	IEEE Oct2013
Materias:	Computer architecture Fault-tolerant computing Multicore processors Distributed shared memory Distributed computing
Acceso en línea:	Ver este registro en EBSCOhost