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Toward Holistic Soft-Error-Resilient Shared-Memory Multicores.

A proposed lightweight, soft-error-resilient architecture for shared-memory multicores enables cores to autonomously perform redundant execution of uninterrupted instruction sequences. The distributed redundancy control mechanism operates in concert with the coherence protocol to provide resiliency...

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Published in:Computer (00189162) Vol. 46; no. 10; pp. 56 - 65
Main Authors: Shi, Qingchuan, Khan, Omer
Format: Article
Published: IEEE Oct2013
Subjects:
Computer architecture
Fault-tolerant computing
Multicore processors
Distributed shared memory
Distributed computing
Online Access:View this record in EBSCOhost
Summary:A proposed lightweight, soft-error-resilient architecture for shared-memory multicores enables cores to autonomously perform redundant execution of uninterrupted instruction sequences. The distributed redundancy control mechanism operates in concert with the coherence protocol to provide resiliency for both computation and communication hardware. The Web extra at http://youtu.be/9A3oiIerI0w is a video interview in which guest editor Srinivas Devadas and author Omer Khan expand on how a proposed lightweight, soft-error-resilient architecture for shared-memory multicores enables cores to autonomously perform redundant execution of uninterrupted instruction sequences.